Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing

Beitrag bei einer Tagung


Details zur Publikation

Autor(en): Witterauf M, Tanase AP, Hannig F, Teich J
Verlag: HiPEAC
Jahr der Veröffentlichung: 2015
Tagungsband: Proceedings of the 11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES)
Seitenbereich: 205-208
ISBN: 978-88-905806-3-5


FAU-Autoren / FAU-Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Tanase, Alexandru-Petru Dr.-Ing.
Sonderforschungsbereich/Transregio 89 Invasives Rechnen
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Witterauf, Michael
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Witterauf, M., Tanase, A.-P., Hannig, F., & Teich, J. (2015). Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing. In Proceedings of the 11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (pp. 205-208). Fiuggi, IT: HiPEAC.

MLA:
Witterauf, Michael, et al. "Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing." Proceedings of the 11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Fiuggi HiPEAC, 2015. 205-208.

BibTeX: 

Zuletzt aktualisiert 2018-10-08 um 05:58