FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs

Beitrag bei einer Tagung
(Originalarbeit)


Details zur Publikation

Autor(en): Echavarria Gutiérrez JA, Wildermann S, Becher A, Teich J, Ziener D
Jahr der Veröffentlichung: 2016
Tagungsband: Proceedings of 2016 International Conference on Field Programmable Technology
Seitenbereich: 213-216
Sprache: Englisch


Abstract


During the design of embedded systems, many design decisions have to be made to trade off between conflicting objectives such as cost, performance, and power. Approximate computing allows to optimize each objective, yet for the sake of accuracy. This means that a functional flaw is allowed to produce an error as long as this is small enough to maintain a feasible operation of the system or guarantee a certain accuracy of the results. In this paper, we propose a new technique for approximate addition optimized for LUT-Based FPGAs with segmented carry chains. Our optimized adder structure is able to a) best exploit artifacts of LUT-Based FPGAs such as unused inputs and b) provide a smaller average error than previously proposed approximate adder structures, as well as c) a reduced critical path delay than dedicated accurate logic in modern FPGAs. We present a novel stochastic error calculus that is able to take into account also non-uniform input distributions and present a detailed comparison of approximate adder structures proposed in literature with our novel LUT-Based approximate arithmetic structure.


FAU-Autoren / FAU-Herausgeber

Becher, Andreas
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Echavarria Gutiérrez, Jorge Alfonso
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Wildermann, Stefan Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Ziener, Daniel Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Echavarria Gutiérrez, J.A., Wildermann, S., Becher, A., Teich, J., & Ziener, D. (2016). FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs. In Proceedings of 2016 International Conference on Field Programmable Technology (pp. 213-216). Xi'an, CN.

MLA:
Echavarria Gutiérrez, Jorge Alfonso, et al. "FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs." Proceedings of the International Conference on Field Programmable Technology (FPT 2016), Xi'an 2016. 213-216.

BibTeX: 

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