Hardware cost analysis for weakly programmable processor arrays

Beitrag bei einer Tagung
(Konferenzbeitrag)


Details zur Publikation

Autorinnen und Autoren: Kissler D, Hannig F, Kupriyanov O, Teich J
Jahr der Veröffentlichung: 2006
Tagungsband: Proceedings of the International Symposium on System-on-Chip (SoC)
Seitenbereich: 179-182
ISBN: 9781424406227


Abstract


Growing complexity and speed requirements in modern application areas such as wireless communication and multimedia in embedded devices demand for flexible and efficient parallel hardware architectures. The inherent parallelism in these application fields has to be reflected at the hardware level to achieve high performance. Coarse-grained reconfigurable architectures support a high degree of parallelism at multiple levels. In this paper technology-independent hardware cost analysis for a new class of highly parameterizable coarse-grained reconfigurable architectures called weakly programmable processor arrays is performed. © 2006 IEEE.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Kissler, D., Hannig, F., Kupriyanov, O., & Teich, J. (2006). Hardware cost analysis for weakly programmable processor arrays. In Proceedings of the International Symposium on System-on-Chip (SoC) (pp. 179-182). Tampere, FI.

MLA:
Kissler, Dmitrij, et al. "Hardware cost analysis for weakly programmable processor arrays." Proceedings of the 2006 International Symposium on System-on-Chip, SOC, Tampere 2006. 179-182.

BibTeX: 

Zuletzt aktualisiert 2018-31-10 um 13:50