Hardware cost analysis for weakly programmable processor arrays

Kissler D, Hannig F, Kupriyanov O, Teich J (2006)


Publication Status: Published

Publication Type: Conference contribution, Conference Contribution

Publication year: 2006

Pages Range: 179-182

Article Number: 4116484

Conference Proceedings Title: Proceedings of the International Symposium on System-on-Chip (SoC)

Event location: Tampere FI

ISBN: 9781424406227

DOI: 10.1109/ISSOC.2006.321996

Abstract

Growing complexity and speed requirements in modern application areas such as wireless communication and multimedia in embedded devices demand for flexible and efficient parallel hardware architectures. The inherent parallelism in these application fields has to be reflected at the hardware level to achieve high performance. Coarse-grained reconfigurable architectures support a high degree of parallelism at multiple levels. In this paper technology-independent hardware cost analysis for a new class of highly parameterizable coarse-grained reconfigurable architectures called weakly programmable processor arrays is performed. © 2006 IEEE.

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APA:

Kissler, D., Hannig, F., Kupriyanov, O., & Teich, J. (2006). Hardware cost analysis for weakly programmable processor arrays. In Proceedings of the International Symposium on System-on-Chip (SoC) (pp. 179-182). Tampere, FI.

MLA:

Kissler, Dmitrij, et al. "Hardware cost analysis for weakly programmable processor arrays." Proceedings of the 2006 International Symposium on System-on-Chip, SOC, Tampere 2006. 179-182.

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