Efficient reconfigurable on-chip buses for fpgas

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Details zur Publikation

Autorinnen und Autoren: Haubelt C, Koch D, Teich J
Jahr der Veröffentlichung: 2008
Tagungsband: Proceedings 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008)
Seitenbereich: 287-290
ISBN: 9780769533070


Abstract


This paper presents techniques for generating on-chip buses suitable for dynamically integrating hardware modules into an FPGA-based SoC by partial reconfiguration. The buses permit direct connections of master and slave modules to the bus in combination with a flexible fine-grained module placement and with minimized latency and area overheads. A test system will demonstrate a transfer rate of 800 MB/s while providing an extreme high placement flexibility. © 2008 IEEE.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Haubelt, Christian Prof. Dr.-Ing.
Technische Fakultät
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Haubelt, C., Koch, D., & Teich, J. (2008). Efficient reconfigurable on-chip buses for fpgas. In Proceedings 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008) (pp. 287-290). Palo Alto, California, US.

MLA:
Haubelt, Christian, Dirk Koch, and Jürgen Teich. "Efficient reconfigurable on-chip buses for fpgas." Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM'08, Palo Alto, California 2008. 287-290.

BibTeX: 

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