Boundary control: A new distributed control architecture for space-time transformed (VLSI) processor arrays

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Details zur Publikation

Autorinnen und Autoren: Bednara M, Hannig F, Teich J
Herausgeber: Matthews M.B.
Jahr der Veröffentlichung: 2001
Band: 1
Tagungsband: Proc. 35th IEEE Asilomar Conf. on Signals, Systems and Computers
Seitenbereich: 468-474


Abstract


We present a new methodology for controlling the space-time behavior of VLSI and FPGA-based processor arrays. The main idea is to generate simple local control elements which take control over the activeness of each attached processor element. Each control element thereby propagates a "start" and a "stop execution" signal to its neighbors. We show that our control mechanism is much more efficient than existing approaches such as [10, 17] because 1) only two control signals (start/stop) are required, 2) no extension of the computation space is necessary. 3) By the local propagation of just one start/stop signal, energy is saved as processing elements are only active between the time they have received the start signal and the time they have received the stop signal. Our methodology is applicable to one- and multi-dimensional processor arrays and is based on local control signal propagation. We provide a theoretical analysis of the overhead caused by the control structure.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Bednara, M., Hannig, F., & Teich, J. (2001). Boundary control: A new distributed control architecture for space-time transformed (VLSI) processor arrays. In Matthews M.B. (Eds.), Proc. 35th IEEE Asilomar Conf. on Signals, Systems and Computers (pp. 468-474). Pacific Grove, CA, US.

MLA:
Bednara, Marcus, Frank Hannig, and Jürgen Teich. "Boundary control: A new distributed control architecture for space-time transformed (VLSI) processor arrays." Proceedings of the 35th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA Ed. Matthews M.B., 2001. 468-474.

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