Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays

Beitrag in einer Fachzeitschrift


Details zur Publikation

Autor(en): Lari V, Muddasani S, Boppu S, Hannig F, Schmid M, Teich J
Zeitschrift: ACM Transactions on Design Automation of Electronic Systems
Verlag: Association for Computing Machinery (ACM)
Jahr der Veröffentlichung: 2012
Band: 18
Heftnummer: 1
Seitenbereich: 1-25
ISSN: 1084-4309


Abstract


We present a self-adaptive hierarchical power management technique for massively parallel processor architectures, supporting a new resource-aware parallel computing paradigm called invasive computing. Here, an application can dynamically claim, execute, and release the resources in three phases: resource acquisition (invade), program loading/configuration and execution (infect), and release (retreat). Resource invasion is governed by dedicated decentralized hardware controllers, called invasion controllers (iCtrls), which are integrated into each processing element (PE). Several invasion strategies for claiming linearly connected or rectangular regions of processing resources are implemented. The key idea is to exploit the decentralized resource management inherent to invasive computing for power savings by enabling applications themselves to control the power for processing resources and invasion controllers using a hierarchical power-gating approach. We propose analytical models for estimating various components of energy consumption for faster design space exploration and compare them with the results obtained from a cycle-accurate C++ simulator of the processor array. In order to find optimal design trade-offs, various parameters like (a) energy consumption, (b) hardware cost, and (c) timing overheads are compared for different sizes of power domains. Experimental results show significant energy savings (up to 73%) for selected characteristical algorithms and different resource utilizations. In addition, we demonstrate the accuracy of our proposed analytical model. Here, estimation errors less than 3.6% can be reported. © 2012 ACM.



FAU-Autoren / FAU-Herausgeber

Boppu, Srinivas
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Lari, Vahid
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Muddasani, Shravan
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Schmid, Moritz
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Lari, V., Muddasani, S., Boppu, S., Hannig, F., Schmid, M., & Teich, J. (2012). Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays. ACM Transactions on Design Automation of Electronic Systems, 18(1), 1-25. https://dx.doi.org/10.1145/2390191.2390193

MLA:
Lari, Vahid, et al. "Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays." ACM Transactions on Design Automation of Electronic Systems 18.1 (2012): 1-25.

BibTeX: 

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