Accelerating design space exploration using Pareto-front arithmetics [SoC design]

Beitrag bei einer Tagung
(Konferenzbeitrag)


Details zur Publikation

Autorinnen und Autoren: Haubelt C, Teich J
Verlag: Institute of Electrical and Electronics Engineers Inc.
Jahr der Veröffentlichung: 2003
Tagungsband: Proceedings ASP-DAC 2003, Asia and South Pacific Design Automation Conference
Seitenbereich: 525-531
ISBN: 0780376595


Abstract


In this paper, we propose an approach for the synthesis of heterogeneous (embedded) systems, while exploiting a hierarchical problem structure. Particular to our approach is that we explore the set of so-called Pareto-optimal solutions, i.e., optimizing multiple objectives simultaneously. Since system complexity grows steadily, leading to giant search spaces which demand new strategies in design space exploration, we propose Pareto-front arithmetics (PFA), using results of subsystems to construct implementations of the top-level system. This way, we are able to reduce the exploration time dramatically. An example of an MPEG4 coder is used to show the benefit of this approach in real-life applications.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Haubelt, Christian Prof. Dr.-Ing.
Technische Fakultät
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Haubelt, C., & Teich, J. (2003). Accelerating design space exploration using Pareto-front arithmetics [SoC design]. In Proceedings ASP-DAC 2003, Asia and South Pacific Design Automation Conference (pp. 525-531). Kitakyushu, JP: Institute of Electrical and Electronics Engineers Inc..

MLA:
Haubelt, Christian, and Jürgen Teich. "Accelerating design space exploration using Pareto-front arithmetics [SoC design]." Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 2003, Kitakyushu Institute of Electrical and Electronics Engineers Inc., 2003. 525-531.

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