A bus-based SoC architecture for flexible module placement on reconfigurable FPGAs

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Details zur Publikation

Autorinnen und Autoren: Oetken A, Wildermann S, Teich J, Koch D
Jahr der Veröffentlichung: 2010
Tagungsband: Proceedings of International Conference on Field-Programmable Logic and Applications (FPL'10)
Seitenbereich: 234-239
ISBN: 9780769541792


Abstract


This paper proposes an FPGA-based System-on-Chip (SoC) architecture with support for dynamic runtime reconfiguration. The SoC is divided into two parts, the static embedded CPU sub-system and the dynamically reconfigurable part. An additional bus system connects the embedded CPU subsystem with modules within the dynamic area, offering a flexible way to communicate among all SoC components. This makes it possible to implement a reconfigurable design with support for free module placement. An enhanced memory access method is included for high-speed access to an external memory. The dynamic part includes a streaming technology which implements a direct connection between reconfigurable modules. The paper describes the architecture and shows the advantages in a smart camera case study. © 2010 IEEE.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Wildermann, Stefan Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Einrichtungen weiterer Autorinnen und Autoren

University of Oslo


Zitierweisen

APA:
Oetken, A., Wildermann, S., Teich, J., & Koch, D. (2010). A bus-based SoC architecture for flexible module placement on reconfigurable FPGAs. In Proceedings of International Conference on Field-Programmable Logic and Applications (FPL'10) (pp. 234-239). Milano, IT.

MLA:
Oetken, Andreas, et al. "A bus-based SoC architecture for flexible module placement on reconfigurable FPGAs." Proceedings of the 20th International Conference on Field Programmable Logic and Applications, FPL 2010, Milano 2010. 234-239.

BibTeX: 

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