Design of low power on-chip processor arrays

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(Konferenzbeitrag)


Details zur Publikation

Autor(en): Lari V, Muddasani S, Boppu S, Hannig F, Teich J
Jahr der Veröffentlichung: 2012
Tagungsband: Proceedings of the 23rd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP)
Seitenbereich: 165-168
ISBN: 9780769547688


Abstract


In this paper, we present an ultra low power design for a class of massively parallel architectures, called tightly-coupled processor arrays.Here, the key idea is to exploit the benefits of a decentralized resource management as inherent to invasive computing for power saving.We propose concepts and studying different architecture trade-offs for hierarchical power management by temporarily shutting down regions of processors through power gating. Moreover, a) overall system chip energy consumption, b) hardware cost, and c) timing overheads are compared for different sizes of power domains.Experimental results show that up to 70% of system energy consumption may be saved for selected characteristical algorithms and different resource utilizations. © 2012 IEEE.



FAU-Autoren / FAU-Herausgeber

Boppu, Srinivas
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Lari, Vahid
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Muddasani, Shravan
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Lari, V., Muddasani, S., Boppu, S., Hannig, F., & Teich, J. (2012). Design of low power on-chip processor arrays. In Proceedings of the 23rd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) (pp. 165-168). Delft, NL.

MLA:
Lari, Vahid, et al. "Design of low power on-chip processor arrays." Proceedings of the 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2012, Delft 2012. 165-168.

BibTeX: 

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