Nano-technology aware investigations on fault-masking techniques in the presence of high fault probabilities

Sand M, Sieh V, Fey D (2010)

Publication Type: Conference contribution

Publication year: 2010

Edited Volumes: Proceedings of the 2010 International Conference on High Performance Computing and Simulation, HPCS 2010

Pages Range: 181-187

Conference Proceedings Title: Proceedings of the 2010 International Conference on High Performance Computing and Simulation (HPCS)

Event location: Caen, France FR

ISBN: 978-1-4244-6827-0

DOI: 10.1109/HPCS.2010.5547139

Abstract

Nano-architectures are promising alternatives for current CMOS technology, which is facing serious challenges for further down-scaling. However, high failure rates - compared to the conventional CMOS process - lead to multiple faults during lifetime operation of nano-architectures. In this paper, we investigate the outcome of traditional fault-masking techniques in the presence of high fault probabilities. Redundant codes and circuit structures are evaluated in a generic way, using stochastic methods. The original goal was to provide a means to decide, under which conditions, which fault-masking techniques are worthwhile. Our results, however, suggest, that these techniques require extremely low fault rates and/or cause extraordinarily high additional cost. ©2010 IEEE.

Authors with CRIS profile

Volkmar Sieh Lehrstuhl für Informatik 4 (Verteilte Systeme und Betriebssysteme) Dietmar Fey Lehrstuhl für Informatik 3 (Rechnerarchitektur)

How to cite

APA:

Sand, M., Sieh, V., & Fey, D. (2010). Nano-technology aware investigations on fault-masking techniques in the presence of high fault probabilities. In Proceedings of the 2010 International Conference on High Performance Computing and Simulation (HPCS) (pp. 181-187). Caen, France, FR.

MLA:

Sand, Matthias, Volkmar Sieh, and Dietmar Fey. "Nano-technology aware investigations on fault-masking techniques in the presence of high fault probabilities." Proceedings of the 2010 International Conference on High Performance Computing and Simulation (HPCS), Caen, France 2010. 181-187.

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