Scalable Signal Processing based on Reconfigurable FPGAs for Satellite Payload Applications

In this paper, we introduce a signal-processing module for a scalable on-board processor. The signal- processing chain of a single module consists of a high-speed ADC and DAC, as well as a high-performance FPGA. All devices are space-grade or radiation hardened by design (RHBD). Each module is capable of direct sampling of frequencies up to 2250 MHz with a maximum bandwidth of 750 MHz. We discuss the system design in detail with reference to standard software-defined radio (SDR) capabilities. As the engineering model (EM), with a space-grade Virtex-5QV FPGA, is available, we present implementation results of the platform, including the LEON3FT soft core inside the FPGA. We then provide a fail-safe method for the remote (re-) configuration of spaceborne FPGAs. Each signal-processing module gathers device status information and monitors data such as temperature, voltage, current, total ionizing dose (TID) and upset rates. A single-event upset (SEU) sensor based on the FPGAs internal block RAM gathers the current upset rates. This information may be used to apply adaptive single-event effect mitigation to maximize resource efficiency and offer an ideal runtime solution. An example of a two-channel on-board processor (OBP), based on the proposed signal-processing module, is the Fraunhofer OBP (FOBP). We equip the FOBP with two signal-processing modules, a power supply module and a radio frequency module. The FOBP is scheduled to be launched in 2020 with the associated Heinrich Hertz communication satellite. In the outlook section, we discuss future signal processing architectures based on next generation radiation tolerant FPGAs.