Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Bednara M, Beyer O, Teich J, Wanka R
Titel Sammelwerk: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Verlag: IEEE
Jahr der Veröffentlichung: 2000
Tagungsband: Proc. ASAP'00, the Int. Conf. on Application Specific Systems, Architectures, and Processors, pp. 299-308, Boston, MA, U.S.A. IEEE Computer Society Press, July 2000Proc. ASAP'00, the Int. Conf. on Application Specific Systems, Architectures, and Processors
Seitenbereich: 299-308


Abstract


Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the low performance, while realizing multiprocessor sorting methods on parallel computers is much too expensive with respect to power consumption, physical weight, and cost. We investigate cost/performance tradeoffs for hybrid sorting algorithms that use a mixture of sequential merge sort and systolic insertion sort techniques. We propose a scalable architecture for integer sorting that consists of a uniprocessor and an FPGA-based parallel systolic co-processor. Speedups obtained analytically and experimentally and depending on hardware (cost) constraints are determined as a function of time constants of the uniprocessor and the co-processor.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Wanka, Rolf Prof. Dr.
Professur für Informatik (Effiziente Algorithmen und Kombinatorische Optimierung)


Einrichtungen weiterer Autorinnen und Autoren

Universität Paderborn


Zitierweisen

APA:
Bednara, M., Beyer, O., Teich, J., & Wanka, R. (2000). Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. In Proc. ASAP'00, the Int. Conf. on Application Specific Systems, Architectures, and Processors, pp. 299-308, Boston, MA, U.S.A. IEEE Computer Society Press, July 2000Proc. ASAP'00, the Int. Conf. on Application Specific Systems, Architectures, and Processors (pp. 299-308). Boston, MA, US: IEEE.

MLA:
Bednara, Marcus, et al. "Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter." Proceedings of the Int. Conf. on Application Specific Systems, Architectures, and Processors, pp. 299-308, Boston, MA, U.S.A. IEEE Computer Society Press, July 2000Proc. ASAP'00, the Int. Conf. on Application Specific Systems, Architectures, and Processors,, Boston, MA IEEE, 2000. 299-308.

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