Modeling of interconnection networks in massively parallel processor architectures

Kupriyanov O, Hannig F, Kissler D, Teich J, Lallet J, Sentieys O, Pillement S (2007)

Publication Status: Published

Publication Type: Conference contribution

Publication year: 2007

Pages Range: 268-282

Conference Proceedings Title: Proceedings of the 20th International Conference on Architecture of Computing Systems (ARCS 2007)

Event location: Zurich CH

ISBN: 9783540712671

URI: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=37249015485&origin=inward

Abstract

In this paper, we present a new concept for modeling of interconnection networks in the field of massively parallel processor embedded architectures. The main focus of the paper is on two interconnection concepts, namely, interconnect-wrapper and DyRIBox definitions of reconfigurable interconnection networks. We compare both interconnection concepts against each other and formally prove their equality. Both concepts allow to model many different reconfigurable inter-processor networks efficiently. Furthermore, we point out how to define the interconnect using an architecture description language for massively parallel processor architectures called MAML. Finally, we demonstrate the pertinence of our approach by modeling and evaluation of different reconfigurable interconnect topologies. © Springer-Verlag Berlin Heidelberg 2007.

Authors with CRIS profile

Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011

How to cite

APA:

Kupriyanov, O., Hannig, F., Kissler, D., Teich, J., Lallet, J., Sentieys, O., & Pillement, S. (2007). Modeling of interconnection networks in massively parallel processor architectures. In Proceedings of the 20th International Conference on Architecture of Computing Systems (ARCS 2007) (pp. 268-282). Zurich, CH.

MLA:

Kupriyanov, Olexiy, et al. "Modeling of interconnection networks in massively parallel processor architectures." Proceedings of the 20th International Conference on Architecture of Computing Systems, ARCS 2007, Zurich 2007. 268-282.

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