High-speed event-driven RTL compiled simulation

Kupriyanov O, Hannig F, Teich J (2004)

Publication Status: Published

Publication Type: Conference contribution

Publication year: 2004

Book Volume: 3133

Pages Range: 519-529

Conference Proceedings Title: Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04)

Event location: Samos GR

URI: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=35048851603&origin=inward

Abstract

In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part of our BUILDABONG [7] framework, which aims at architecture and compiler co-generation for special purpose processors. The main focus of the paper is on the transformation of a given architecture's circuit into a graph and applying on it an essential graph decomposition algorithm to transform the graph into subgraphs denoting the minimal subsets of sequential elements which have to be reevaluated during each simulation cycle. As a second optimization, we present a partitioning algorithm, which introduces intermediate registers to minimize the number of evaluations of combinational nodes during a simulation cycle. The simulator's superior performance compared to an existing commercial simulator is shown. Finally, we demonstrate the pertinence of our approach by simulating a MIPS processor. © Springer-Verlag Berlin Heidelberg 2004.

Authors with CRIS profile

Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

How to cite

APA:

Kupriyanov, O., Hannig, F., & Teich, J. (2004). High-speed event-driven RTL compiled simulation. In Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04) (pp. 519-529). Samos, GR.

MLA:

Kupriyanov, Olexiy, Frank Hannig, and Jürgen Teich. "High-speed event-driven RTL compiled simulation." Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04), Samos 2004. 519-529.

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