Energy Estimation of Nested Loop Programs

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Hannig F, Teich J
Titel Sammelwerk: Annual ACM Symposium on Parallel Algorithms and Architectures
Jahr der Veröffentlichung: 2002
Tagungsband: Proceedings 14th Annual ACM Symposium on Parallel Algorithms and Architectures


Abstract


An energy estimation methodology when mapping nested loop programs onto fine grained VLSI architectures is proposed. Regular loop algorithms with uniform data dependencies have some power consumption-friendly properties. E.g., using linear allocation and scheduling functions (loop transformations) results in distributed computations and communication between nearest neighbor processors. So, data can be stored locally in each processor which is essential for low power VLSI designs. We show that the chosen mapping has a significant influence on the consumed energy. Our estimation approach identifies statements with decreased operand switching activity. For these statements with reduced activity, a lower power consumption value can be directly obtained from a generated table based model to refine the estimation. Experimental results fortify the significant influence of the mapping (loop transformation).



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Hannig, F., & Teich, J. (2002). Energy Estimation of Nested Loop Programs. In Proceedings 14th Annual ACM Symposium on Parallel Algorithms and Architectures. Winnipeg, Manitoba, CA.

MLA:
Hannig, Frank, and Jürgen Teich. "Energy Estimation of Nested Loop Programs." Proceedings of the 14th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA 2002),, Winnipeg, Manitoba 2002.

BibTeX: 

Zuletzt aktualisiert 2018-08-08 um 04:35