Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism

Schaffer R, Merker R, Hannig F, Teich J (2008)

Publication Type: Conference contribution

Publication year: 2008

Publisher: IEEE Press

Edited Volumes: Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008

City/Town: New York

Pages Range: 391-398

Conference Proceedings Title: Proceedings of the 11th Euromicro Conference on Digital System Design

Event location: Parma IT

DOI: 10.1109/DSD.2008.24

Abstract

In this paper a systematic mapping method for a specific algorithm class is given which exploits all levels of parallelism of the target architecture. This target architecture is a processor array where each processing element can have several functional units. This functional units allow subword parallelism, that means multiple equal operations with low data word width can be executed in parallel in the data path of the functional units. The mapping method is illustrated on the edge detection algorithm, and achieves up to 99% of the theoretical speed-up. © 2008 IEEE.

Authors with CRIS profile

Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011 Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

Involved external institutions

Technische Universität Dresden DE Germany (DE)

How to cite

APA:

Schaffer, R., Merker, R., Hannig, F., & Teich, J. (2008). Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. In Proceedings of the 11th Euromicro Conference on Digital System Design (pp. 391-398). Parma, IT: New York: IEEE Press.

MLA:

Schaffer, Rainer, et al. "Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism." Proceedings of the 11th Euromicro Conference on Digital System Design (DSD), Parma New York: IEEE Press, 2008. 391-398.

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