Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Schaffer R, Merker R, Hannig F, Teich J
Titel Sammelwerk: Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008
Verlag: IEEE Press
Verlagsort: New York
Jahr der Veröffentlichung: 2008
Tagungsband: Proceedings of the 11th Euromicro Conference on Digital System Design
Seitenbereich: 391-398


Abstract


In this paper a systematic mapping method for a specific algorithm class is given which exploits all levels of parallelism of the target architecture. This target architecture is a processor array where each processing element can have several functional units. This functional units allow subword parallelism, that means multiple equal operations with low data word width can be executed in parallel in the data path of the functional units. The mapping method is illustrated on the edge detection algorithm, and achieves up to 99% of the theoretical speed-up. © 2008 IEEE.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Einrichtungen weiterer Autorinnen und Autoren

Technische Universität Dresden


Zitierweisen

APA:
Schaffer, R., Merker, R., Hannig, F., & Teich, J. (2008). Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. In Proceedings of the 11th Euromicro Conference on Digital System Design (pp. 391-398). Parma, IT: New York: IEEE Press.

MLA:
Schaffer, Rainer, et al. "Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism." Proceedings of the 11th Euromicro Conference on Digital System Design (DSD), Parma New York: IEEE Press, 2008. 391-398.

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