Automatic FIR Filter Generation for FPGAs

Beitrag bei einer Tagung

Details zur Publikation

Autor(en): Dutta H, Hannig F, Teich J
Titel Sammelwerk: Lecture Notes in Computer Science
Verlag: Springer-verlag
Verlagsort: Berlin, Heidelberg, New York
Jahr der Veröffentlichung: 2005
Titel der Reihe: Lecture Notes in Computer Science (LNCS)
Band: 3553
Tagungsband: In Proceedings of the 5th International Workshop on Embedded Computer Systems, Architectures, Modeling, and Simulation (SAMOS 2005)
Seitenbereich: 51-61
ISBN: 3-540-26969-X
ISSN: 0302-9743


This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. PARO is a design system project for modeling, transformation, optimization, and synthesis of massively parallel VLSI architectures. The FIR filter generator employs during the design flow the following advanced transformations, (a) hierarchical partitioning in order to balance the amount of local memory with external communication, and (b), partial localization to achieve higher throughput and smaller latencies. Furthermore, our filter generator allows for design space exploration to tackle trade-offs in cost and speed. Finally, synthesizable VHDL code is generated and mapped to an FPGA, the results are compared with a commercial filter generator. © Springer-Verlag Berlin Heidelberg 2005.

FAU-Autoren / FAU-Herausgeber

Dutta, Hritam
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Zuletzt aktualisiert 2018-09-08 um 21:55