Optimization of Dynamic Hardware Reconfigurations

Beitrag in einer Fachzeitschrift


Details zur Publikation

Autorinnen und Autoren: Fekete SP, Schepers J, Teich J
Zeitschrift: Journal of Supercomputing
Verlag: Springer Verlag (Germany)
Jahr der Veröffentlichung: 2001
Heftnummer: Vol. 19, No. 1
Seitenbereich: 57-75
ISSN: 0920-8542


Abstract


Recent generations of Field Programmable Gate Arrays (FPGA) allow the dynamic reconfiguration of cells on the chip during run-time. For a given problem consisting of a set of tasks with computation requirements modeled by rectangles of cells, several optimization problems such as finding the array of minimal size to accomplish the tasks within a given time limit are considered. Existing approaches based on ILP formulations to solve these problems as multi-dimensional packing problems turn out not to be applicable for problem sizes of interest. Here, a breakthrough is achieved in solving these problems to optimality by using the new notion of packing classes. It allows a significant reduction of the search space such that problems of the above type may be solved exactly using a special branch-and-bound technique. We validate the usefulness of our method by providing computational results.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Einrichtungen weiterer Autorinnen und Autoren

Technische Universität Braunschweig


Zitierweisen

APA:
Fekete, S.P., Schepers, J., & Teich, J. (2001). Optimization of Dynamic Hardware Reconfigurations. Journal of Supercomputing, Vol. 19, No. 1, 57-75. https://dx.doi.org/10.1023/A:1011188411132

MLA:
Fekete, Sandor P., Jörg Schepers, and Jürgen Teich. "Optimization of Dynamic Hardware Reconfigurations." Journal of Supercomputing Vol. 19, No. 1 (2001): 57-75.

BibTeX: 

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