Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Dutta H, Hannig F, Teich J
Titel Sammelwerk: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Verlag: Springer-verlag
Jahr der Veröffentlichung: 2009
Titel der Reihe: Lecture Notes in Computer Science (LNCS)
Band: 5455
Tagungsband: Proceedings of the 22nd International Conference on Architecture of Computing Systems
Seitenbereich: 233-245
ISBN: 978-3-642-00453-7
ISSN: 0302-9743


Abstract


In order to meet demanding challenges of increasing computational requirements and stringent power constraints, there is a gradual trend towards heterogeneous multi-processor system-on-chip (MPSoC) designs integrating application specific acceleration engines. One major problem faced by the design tools for mapping of algorithms onto MPSoC architectures is the dimensioning of system components through performance analysis. In this paper, we propose a fast and accurate methodology for rate matching of statically scheduled acceleration engines using modular performance analysis. Given a set of Pareto-optimal hardware accelerator designs and an input workload behavior, the proposed methodology determines cost efficient hardware accelerators that can handle the workload. A motion JPEG case study illustrates the benefit of coupling high level synthesis tools with performance analysis. © 2009 Springer Berlin Heidelberg.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Dutta, Hritam
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Dutta, H., Hannig, F., & Teich, J. (2009). Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis. In Proceedings of the 22nd International Conference on Architecture of Computing Systems (pp. 233-245). Delft, NL: Springer-verlag.

MLA:
Dutta, Hritam, Frank Hannig, and Jürgen Teich. "Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis." Proceedings of the 22nd International Conference on Architecture of Computing Systems (ARCS), Delft Springer-verlag, 2009. 233-245.

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