A system-level approach to hardware reconfigurable systems

Beitrag bei einer Tagung
(Konferenzbeitrag)


Details zur Publikation

Autorinnen und Autoren: Haubelt C, Otto S, Grabbe C, Teich J
Jahr der Veröffentlichung: 2005
Band: 1
Tagungsband: Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'05)
Seitenbereich: 298-301
ISBN: 9780780387362


Abstract


There is trend towards networked and distributed hardware reconfigurable systems, complicating the design process at the system-level. This paper will provide a solution to the problem of design space exploration for such embedded systems of the next generation. We will show the problems occurring while exploring the design space at the system-level, leading to new properties for valid implementations. The novelty of this approach lies in the support of explicit communication modeling and time-multiplexed architecture modeling in a single model. The proposed design space exploration is based on Evolutionary Algorithms and a new slack-based list scheduler. © 2005 IEEE.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Haubelt, Christian Prof. Dr.-Ing.
Technische Fakultät
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Haubelt, C., Otto, S., Grabbe, C., & Teich, J. (2005). A system-level approach to hardware reconfigurable systems. In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'05) (pp. 298-301). Shanghai, CN.

MLA:
Haubelt, Christian, et al. "A system-level approach to hardware reconfigurable systems." Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai 2005. 298-301.

BibTeX: 

Zuletzt aktualisiert 2018-08-08 um 00:46