Performance Analysis of Mixed Asynchronous-Synchronous Systems

Beitrag bei einer Tagung


Details zur Publikation

Autor(en): Martin M, Sriram S, Teich J, Thiele L
Titel Sammelwerk: IEEE Workshop on VLSI Signal Processing, Proceedings
Jahr der Veröffentlichung: 1994
Titel der Reihe: IEEE VLSI Signal Processing VII
Tagungsband: Proc. of the IEEE Int. Workshop on VLSI Signal Processing 94
Seitenbereich: 103-112


Abstract


The paper is concerned with the timing analysis of a class digital systems we call mixed asynchronous-synchronous systems. In such a system, each computation module is either synchronous (i.e. clocked) or asynchronous (i.e. selftimed). The communication between modules is assumed to be selftimed for all modules. We introduce a graph model called MASS for describing the timing behaviour of such architectures. The graph contains two kinds of nodes, synchronous and asynchronous nodes. The operation model of a MASS is similar to that of a timed marked graph, however, additional schedule constraints are imposed on synchronous nodes: A synchronous node can only fire at ticks of its local module clock. We analyze the behaviour of MASS, in particular period, periodicity and maximal throughput rate.



FAU-Autoren / FAU-Herausgeber

Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Autor(en) der externen Einrichtung(en)
Eidgenössische Technische Hochschule Zürich (ETHZ) / Swiss Federal Institute of Technology in Zurich


Zitierweisen

APA:
Martin, M., Sriram, S., Teich, J., & Thiele, L. (1994). Performance Analysis of Mixed Asynchronous-Synchronous Systems. In Proc. of the IEEE Int. Workshop on VLSI Signal Processing 94 (pp. 103-112).

MLA:
Martin, Michael, et al. "Performance Analysis of Mixed Asynchronous-Synchronous Systems." Proceedings of the EEE Int. Workshop on VLSI Signal Processing 94 1994. 103-112.

BibTeX: 

Zuletzt aktualisiert 2018-09-08 um 21:08