Automatic Optimization of Hardware Accelerators for Image Processing

Reiche O, Häublein K, Reichenbach M, Hannig F, Teich J, Fey D (2015)

Publication Type: Conference contribution

Publication year: 2015

Pages Range: 10-15

Conference Proceedings Title: Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015)

Event location: Grenoble FR

URI: http://arxiv.org/abs/1502.07448

Abstract

In the domain of image processing, often real-time constraints are required. In particular, in safety-critical applications, such as X-ray computed tomography in medical imaging or advanced driver assistance systems in the automotive domain, timing is of utmost importance. A common approach to maintain real-time capabilities of compute-intensive applications is to offload those computations to dedicated accelerator hardware, such as Field Programmable Gate Arrays (FPGAs). Programming such architectures is a challenging task, with respect to the typical FPGA-specific design criteria: Achievable overall algorithm latency and resource usage of FPGA primitives (BRAM, FF, LUT, and DSP). High-Level Synthesis (HLS) dramatically simplifies this task by enabling the description of algorithms in well-known higher languages (C/C++) and its automatic synthesis that can be accomplished by HLS tools. However, algorithm developers still need expert knowledge about the target architecture, in order to achieve satisfying results. Therefore, in previous work, we have shown that elevating the description of image algorithms to an even higher abstraction level, by using a Domain-Specific Language (DSL), can significantly cut down the complexity for designing such algorithms for FPGAs. To give the developer even more control over the common trade-off, latency vs. resource usage, we will present an automatic optimization process where these criteria are analyzed and fed back to the DSL compiler, in order to generate code that is closer to the desired design specifications. Finally, we generate code for stereo block matching algorithms and compare it with hand

Authors with CRIS profile

Oliver Reiche Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Konrad Häublein Lehrstuhl für Informatik 3 (Rechnerarchitektur) Marc Reichenbach Lehrstuhl für Informatik 3 (Rechnerarchitektur) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Dietmar Fey Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Related research project(s)

GRK 1773: Heterogeneous Image Systems, Project B3 (GRK 1773) RTG 1773: Heterogeneous Image Systems Oct. 1, 2012 - March 31, 2017 A Domain-Specific Language and GPU Target Code Generator for Image Processing Applications (HIPAcc) Jan. 1, 2009 - Jan. 1, 2012

How to cite

APA:

Reiche, O., Häublein, K., Reichenbach, M., Hannig, F., Teich, J., & Fey, D. (2015). Automatic Optimization of Hardware Accelerators for Image Processing. In Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) (pp. 10-15). Grenoble, FR.

MLA:

Reiche, Oliver, et al. "Automatic Optimization of Hardware Accelerators for Image Processing." Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015), Grenoble 2015. 10-15.

BibTeX: Download