Massively Parallel Processor Architectures for Resource-aware Computing
Beitrag bei einer Tagung
Details zur Publikation
Autor(en): Lari V, Tanase AP, Hannig F, Teich J
Jahr der Veröffentlichung: 2014
Tagungsband: Proc. of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014)
Seitenbereich: 1-7
FAU-Autoren / FAU-Herausgeber
| Hannig, Frank PD Dr.-Ing. |
| | Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) |
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| | | Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) |
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| Tanase, Alexandru-Petru Dr.-Ing. |
| | Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) |
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| Teich, Jürgen Prof. Dr.-Ing. |
| | Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) |
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Zitierweisen
APA: | Lari, V., Tanase, A.-P., Hannig, F., & Teich, J. (2014). Massively Parallel Processor Architectures for Resource-aware Computing. In Proc. of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014) (pp. 1-7). Paderborn, DE. |
MLA: | Lari, Vahid, et al. "Massively Parallel Processor Architectures for Resource-aware Computing." Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing ), Paderborn 2014. 1-7. |