System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures

Hannig F, Schmid M, Lari V, Boppu S, Teich J (2013)

Publication Type: Conference contribution

Publication year: 2013

Publisher: ACM Press

Edited Volumes: Proceedings of the ACM International Conference on Computing Frontiers, CF 2013

City/Town: New York, NY, USA

Pages Range: 1-4

Conference Proceedings Title: Proc. ACM International Conference on Computing Frontiers

Event location: Ischia

ISBN: 978-1-4503-2053-5

DOI: 10.1145/2482767.2482770

Abstract

As data locality is a key factor for the acceleration of loop programs on processor arrays, we propose a buffer architecture that can be configured at run-time to select between different schemes for memory access. In addition to traditional address-based memory banks, the buffer architecture can deliver data in a streaming manner to the processing elements of the array, which supports dense and sparse stencil operations. Moreover, to minimize data transfers to the buffers, the design contains an interlinked mode, which is especially targeted at 2-D kernel computations. The buffers can be used individually to achieve high data throughput by utilizing a maximum number of I/O channels to the array, or concatenated to provide higher storage capacity at a reduced amount of I/O channels. Copyright 2013 ACM.

Authors with CRIS profile

Related research project(s)

How to cite

APA:

Hannig, F., Schmid, M., Lari, V., Boppu, S., & Teich, J. (2013). System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures. In Proc. ACM International Conference on Computing Frontiers (pp. 1-4). Ischia, IT: New York, NY, USA: ACM Press.

MLA:

Hannig, Frank, et al. "System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures." Proceedings of the ACM International Conference on Computing Frontiers (CF), Ischia New York, NY, USA: ACM Press, 2013. 1-4.

BibTeX: Download