Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators

Boppu S, Hannig F, Teich J (2013)

Publication Type: Conference contribution

Publication year: 2013

Journal

International Conference on Application-Specific Systems, Architectures and Processors, Proceedings Institute of Electrical and Electronics Engineers

Publisher: Institute of Electrical and Electronics Engineers

Edited Volumes: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

City/Town: New York, NY, USA

Pages Range: 10-17

Conference Proceedings Title: Proc. 24th International Conference on Application-Specific Systems, Architectures and Processors

Event location: Washington, DC US

ISBN: 978-1-4799-0493-8

DOI: 10.1109/ASAP.2013.6567544

Abstract

We present a novel design methodology for the mapping of nested loops onto programmable hardware accelerators. Key features of our approach are: (1) Design entry in form of a functional programming language and loop parallelization in the polyhedron model, (2) the underlying accelerator architectures consist of lightweight, tightly-coupled, and programmable processor arrays, which can exploit both loop-level parallelism and instruction-level parallelism, (3) support of zero-overhead looping not only for inner most loops but also for arbitrarily nested loops. We implemented the proposed methodology in a prototype design tool and evaluated selected benchmarks by comparing our code generator with the Trimaran compilation framework. As the results show, our approach can reduce the size of the generated processor codes up to 64% while at the same time achieving a significant higher throughput. © 2013 IEEE.

Authors with CRIS profile

Srinivas Boppu Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

How to cite

APA:

Boppu, S., Hannig, F., & Teich, J. (2013). Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators. In Proc. 24th International Conference on Application-Specific Systems, Architectures and Processors (pp. 10-17). Washington, DC, US: New York, NY, USA: Institute of Electrical and Electronics Engineers.

MLA:

Boppu, Srinivas, Frank Hannig, and Jürgen Teich. "Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators." Proceedings of the 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Washington, DC New York, NY, USA: Institute of Electrical and Electronics Engineers, 2013. 10-17.

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