Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines

Dutta H, Zhai J, Hannig F, Teich J (2009)

Publication Type: Conference contribution

Publication year: 2009

Pages Range: 161-168

Conference Proceedings Title: Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors

Event location: Boston, MA US

ISBN: 978-0-7695-3732-0

Authors with CRIS profile

Hritam Dutta Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011 Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

How to cite

APA:

Dutta, H., Zhai, J., Hannig, F., & Teich, J. (2009). Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines. In Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (pp. 161-168). Boston, MA, US.

MLA:

Dutta, Hritam, et al. "Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines." Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), Boston, MA 2009. 161-168.

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