A Configurable VHDL Template for Parallelization of 3D Stencil Codes on FPGAs

Richter F, Schmidt M, Fey D (2012)

Publication Type: Conference contribution, Conference Contribution

Publication year: 2012

Publisher: CSREA Press

City/Town: Las Vegas

Book Volume: 1

Pages Range: 48-55

Edition: 1

Conference Proceedings Title: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms

Event location: Las Vegas

ISBN: 1-60132-233-X

Authors with CRIS profile

Franz Richter-Gottfried Lehrstuhl für Informatik 3 (Rechnerarchitektur) Michael Schmidt Lehrstuhl für Informatik 3 (Rechnerarchitektur) Dietmar Fey Lehrstuhl für Informatik 3 (Rechnerarchitektur)

How to cite

APA:

Richter, F., Schmidt, M., & Fey, D. (2012). A Configurable VHDL Template for Parallelization of 3D Stencil Codes on FPGAs. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (pp. 48-55). Las Vegas: Las Vegas: CSREA Press.

MLA:

Richter, Franz, Michael Schmidt, and Dietmar Fey. "A Configurable VHDL Template for Parallelization of 3D Stencil Codes on FPGAs." Proceedings of the ERSA'12, Las Vegas Las Vegas: CSREA Press, 2012. 48-55.

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