Bitonic Sorting on Dynamically Reconfigurable Architectures

Conference contribution


Publication Details

Author(s): Angermeier J, Sibirko E, Wanka R, Teich J
Title edited volumes: IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum
Publisher: IEEE Press
Publishing place: New York, NY, USA
Publication year: 2011
Conference Proceedings Title: Proc. IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)
Pages range: 314-317
ISBN: 978-1-61284-425-1


Abstract


Sorting is one of the most investigated tasks computers are used for. Up to now, not much research has been put into increasing the flexibility and performance of sorting applications by applying reconfigurable computer systems. There are parallel sorting algorithms (sorting circuits) which are highly suitable for VLSI hardware realization and which outperform sequential sorting methods applied on traditional software processors by far. But usually they require a large area that increases with the number of keys to be sorted. This drawback concerns ASIC and statically reconfigurable systems. In this paper, we present a way to adopt the well-known Bitonic sorting method to dynamically reconfigurable systems such that this drawback is overcome. We present a detailed description of the design and actual implementation, and we present experimental results of our approach to show its benefits in performance and the trade-offs of our approach. © 2011 IEEE.



FAU Authors / FAU Editors

Angermeier, Josef Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Wanka, Rolf Prof. Dr.
Professur für Informatik (Effiziente Algorithmen und Kombinatorische Optimierung)


How to cite

APA:
Angermeier, J., Sibirko, E., Wanka, R., & Teich, J. (2011). Bitonic Sorting on Dynamically Reconfigurable Architectures. In Proc. IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW) (pp. 314-317). Anchorage, AL, US: New York, NY, USA: IEEE Press.

MLA:
Angermeier, Josef, et al. "Bitonic Sorting on Dynamically Reconfigurable Architectures." Proceedings of the IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), Anchorage, AL New York, NY, USA: IEEE Press, 2011. 314-317.

BibTeX: 

Last updated on 2018-09-08 at 22:54