Introducing a Performance Model for Bandwidth-Limited Loop Kernels

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Eitzinger J, Hager G
Titel Sammelwerk: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Verlag: Springer-verlag
Verlagsort: Berlin Heidelberg
Jahr der Veröffentlichung: 2010
Titel der Reihe: Lecture Notes in Computer Science
Band: 6067
Tagungsband: Parallel Processing and Applied Mathematics
Seitenbereich: 615-624
ISSN: 0302-9743


Abstract


We present a diagnostic performance model for bandwidth-limited loop kernels which is founded on the analysis of modern cache based microarchitectures. This model allows an accurate performance prediction and evaluation for existing instruction codes. It provides an in-depth understanding of how performance for different memory hierarchy levels is made up. The performance of raw memory load, store and copy operations and a stream vector triad are analyzed and benchmarked on three modern x86-type quad-core architectures in order to demonstrate the capabilities of the model. © 2010 Springer-Verlag Berlin Heidelberg.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Eitzinger, Jan Dr.
Regionales Rechenzentrum Erlangen (RRZE)
Hager, Georg Dr.
Regionales Rechenzentrum Erlangen (RRZE)


Zitierweisen

APA:
Eitzinger, J., & Hager, G. (2010). Introducing a Performance Model for Bandwidth-Limited Loop Kernels. In Parallel Processing and Applied Mathematics (pp. 615-624). Wroclaw, Poland, PL: Berlin Heidelberg: Springer-verlag.

MLA:
Eitzinger, Jan, and Georg Hager. "Introducing a Performance Model for Bandwidth-Limited Loop Kernels." Proceedings of the 8th International Conference, PPAM 2009 , Revised Selected Papers, Part I, Wroclaw, Poland Berlin Heidelberg: Springer-verlag, 2010. 615-624.

BibTeX: 

Zuletzt aktualisiert 2018-09-08 um 22:39