Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Hannig F, Dutta H, Teich J
Titel Sammelwerk: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Verlag: Springer-verlag
Jahr der Veröffentlichung: 2009
Titel der Reihe: Lecture Notes in Computer Science (LNCS)
Band: 5455
Tagungsband: Proceedings of the 22nd International Conference on Architecture of Computing Systems
Seitenbereich: 16-27
ISBN: 978-3-642-00453-7
ISSN: 0302-9743


Abstract


State-of-the-art behavioral synthesis tools barely have high-level transformations in order to achieve highly parallelized implementations. If any, they apply loop unrolling to obtain a higher throughput. In this paper, we employ the PARO behavioral synthesis tool which has the unique ability to perform both loop unrolling or loop partitioning. Loop unrolling replicates the loop kernel and exposes the parallelism for hardware implementation, whereas partitioning tiles the loop program onto a regular array consisting of tightly coupled processing elements. The usage of the same design tool for both the variants enables for the first time, a quantitative evaluation of the two approaches for reconfigurable architectures with help of computationally intensive algorithms selected from different benchmarks. Superlinear speedups in terms of throughput are accomplished for the processor array approach. In addition, area and power cost are reduced. © 2009 Springer Berlin Heidelberg.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Dutta, Hritam
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Hannig, F., Dutta, H., & Teich, J. (2009). Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning. In Proceedings of the 22nd International Conference on Architecture of Computing Systems (pp. 16-27). Delft, NL: Springer-verlag.

MLA:
Hannig, Frank, Hritam Dutta, and Jürgen Teich. "Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning." Proceedings of the 22nd International Conference on Architecture of Computing Systems (ARCS), Delft Springer-verlag, 2009. 16-27.

BibTeX: 

Zuletzt aktualisiert 2018-09-08 um 22:38