Optimal Placement-aware Trace-based Scheduling of Hardware Reconfigurations for FPGA Accelerators

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Sim JE, Wong WF, Teich J
Titel Sammelwerk: Proceedings - IEEE Symposium on Field Programmable Custom Computing Machines, FCCM 2009
Jahr der Veröffentlichung: 2009
Tagungsband: Proc. 17th IEEE Symposium on Field Programmable Custom Computing Machines
Seitenbereich: 279-282


Abstract


Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, we present a polynomial time algorithm for scheduling reconfiguration tasks given a trace of actors (invocations of hardware kernels) that is both provably optimal and placement-aware. In addition, we will propose a dependence analysis to determine whether for each actor instance, a reconfiguration task is needed prior to its execution in hardware. A case study using the H.264 encoder is presented to compare our algorithm against the state-of-the-art heuristics. © 2009 IEEE.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Einrichtungen weiterer Autorinnen und Autoren

National University of Singapore (NUS)


Zitierweisen

APA:
Sim, J.E., Wong, W.-F., & Teich, J. (2009). Optimal Placement-aware Trace-based Scheduling of Hardware Reconfigurations for FPGA Accelerators. In Proc. 17th IEEE Symposium on Field Programmable Custom Computing Machines (pp. 279-282). Napa, CA, US.

MLA:
Sim, Joon Edward, Weng-Fai Wong, and Jürgen Teich. "Optimal Placement-aware Trace-based Scheduling of Hardware Reconfigurations for FPGA Accelerators." Proceedings of the 17th IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'09), Napa, CA 2009. 279-282.

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