PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Dutta H, Hannig F, Ruckdeschel H, Teich J
Titel Sammelwerk: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Verlag: Springer-verlag
Verlagsort: Berlin Heidelberg
Jahr der Veröffentlichung: 2008
Titel der Reihe: Lecture Notes in Computer Science (LNCS)
Tagungsband: Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing
Seitenbereich: 287-293
ISSN: 0302-9743


Abstract


In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications. Key features of PARO are: (1) The design entry in form of a compact and intuitive functional programming language which allows highly parallel implementations. (2) Advanced partitioning techniques are applied in order to balance the trade-offs in cost and performance along with requisite throughputs. This is obtained by distributing computations onto an array of tightly coupled processor elements. (3) We demonstrate the performance of the FPGA synthesized hardware with several selected algorithms from different benchmarks. © 2008 Springer-Verlag Berlin Heidelberg.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Dutta, Hritam
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Dutta, H., Hannig, F., Ruckdeschel, H., & Teich, J. (2008). PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. In Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (pp. 287-293). London, GB: Berlin Heidelberg: Springer-verlag.

MLA:
Dutta, Hritam, et al. "PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications." Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (ARC), London Berlin Heidelberg: Springer-verlag, 2008. 287-293.

BibTeX: 

Zuletzt aktualisiert 2018-09-08 um 22:24