PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications

Hannig F, Ruckdeschel H, Dutta H, Teich J (2008)

Publication Type: Conference contribution

Publication year: 2008

Journal

Lecture Notes in Computer Science Springer Verlag

Publisher: Springer-verlag

Edited Volumes: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Series: Lecture Notes in Computer Science (LNCS)

City/Town: Berlin Heidelberg

Pages Range: 287-293

Conference Proceedings Title: Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing

Event location: London GB

DOI: 10.1007/978-3-540-78610-8_30

Abstract

In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications. Key features of PARO are: (1) The design entry in form of a compact and intuitive functional programming language which allows highly parallel implementations. (2) Advanced partitioning techniques are applied in order to balance the trade-offs in cost and performance along with requisite throughputs. This is obtained by distributing computations onto an array of tightly coupled processor elements. (3) We demonstrate the performance of the FPGA synthesized hardware with several selected algorithms from different benchmarks. © 2008 Springer-Verlag Berlin Heidelberg.

Authors with CRIS profile

Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Hritam Dutta Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

How to cite

APA:

Hannig, F., Ruckdeschel, H., Dutta, H., & Teich, J. (2008). PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. In Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (pp. 287-293). London, GB: Berlin Heidelberg: Springer-verlag.

MLA:

Hannig, Frank, et al. "PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications." Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (ARC), London Berlin Heidelberg: Springer-verlag, 2008. 287-293.

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