Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Wolinski C, Kuchcinski K, Teich J, Hannig F
Titel Sammelwerk: Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008
Verlag: IEEE Press
Verlagsort: New York
Jahr der Veröffentlichung: 2008
Tagungsband: Proceedings of the 11th Euromicro Conference on Digital System Design
Seitenbereich: 345-352


Abstract


In this paper, we introduce a constraint programming-based approach for optimization of routing and reconfiguration overhead for a class of reconfigurable processor array architectures called weakly programmable. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for optimal routing of data between processors as well as for minimization of the routing area and the reconfiguration overhead when switching between the execution of these algorithms. In fact, applying the switching can be accomplished in just a few clock cycles. Our experiments confirm that our method can minimize routing overhead and reduce reconfiguration time significantly. © 2008 IEEE.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Einrichtungen weiterer Autorinnen und Autoren

Université de Rennes 1 / University of Rennes 1


Zitierweisen

APA:
Wolinski, C., Kuchcinski, K., Teich, J., & Hannig, F. (2008). Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. In Proceedings of the 11th Euromicro Conference on Digital System Design (pp. 345-352). Parma, IT: New York: IEEE Press.

MLA:
Wolinski, Christophe, et al. "Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures." Proceedings of the 11th Euromicro Conference on Digital System Design (DSD), Parma New York: IEEE Press, 2008. 345-352.

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Zuletzt aktualisiert 2018-09-08 um 22:24