Co-Design Architecture and Implementation for Point-Based Rendering on FPGAs

Angermeier J, Hanke S, Majer M, Teich J, Wildermann S (2008)

Publication Type: Conference contribution

Publication year: 2008

Edited Volumes: Proceedings The 19th IEEE/IFIP International Symposium on Rapid System Prototyping - Shortening the Path from Specification to Prototype, RSP 2008

Pages Range: 142-148

Conference Proceedings Title: Proc. 19th IEEE/IFIP International Symposium on Rapid System Prototyping

Event location: Monterey US

DOI: 10.1109/RSP.2008.23

Abstract

Current graphic cards include advanced graphic processing units to accelerate the rendering of 3D objects with millions of polygons. As object models grow in complexity, the rendering approach based on points as primitives is regarded superior in terms of scalability and efficiency. Next generation graphic cards could contain reconfigurable fabrics, similar to those implemented in current FPGAs, to offer two advantages: a) fast rendering units and b) new mechanisms for custom, run-time exchangeable accelerators. In this paper, we propose a hardware point-rendering architecture tailored specifically for reconfigurable systems. The presented implementation on a real FPGA-based platform demonstrates on the one hand the effectiveness of the approach and on the other hand it provides valuable insights into possible future improvements for this problem scenario. © 2008 IEEE. DOI 10.1109/RSP.2008.23.

Authors with CRIS profile

Josef Angermeier Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Stefan Wildermann Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

How to cite

APA:

Angermeier, J., Hanke, S., Majer, M., Teich, J., & Wildermann, S. (2008). Co-Design Architecture and Implementation for Point-Based Rendering on FPGAs. In Proc. 19th IEEE/IFIP International Symposium on Rapid System Prototyping (pp. 142-148). Monterey, US.

MLA:

Angermeier, Josef, et al. "Co-Design Architecture and Implementation for Point-Based Rendering on FPGAs." Proceedings of the Proc. 19th IEEE/IFIP International Symposium on Rapid System Prototyping (RSP ), Monterey 2008. 142-148.

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