Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Hannig F, Kuchcinski K, Teich J, Wolinski C
Titel Sammelwerk: Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL
Verlag: IEEE Press
Verlagsort: New York
Jahr der Veröffentlichung: 2008
Tagungsband: Proceedings of the International Conference on Field Programmable Logic and Applications
Seitenbereich: 391-396


Abstract


In this paper, we introduce a constraint programming-based approach for the optimization of area and of reconfiguration time for communication networks for a class of regular 2D reconfigurable processor array architectures. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for the optimal routing of data between processors. Here, we support also multi-casting data transfers for the first time. The routing found by our method minimizes the area or the reconfiguration time of the communication network, when switching between the execution of these algorithms. In fact, when switching, the communication network reconfiguration can be executed in just a few clock cycles. Moreover the communication network area can be minimized significantly (62% in average). ©2008 IEEE.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Einrichtungen weiterer Autorinnen und Autoren

Lund University / Lunds universitet
Université de Rennes 1 / University of Rennes 1


Zitierweisen

APA:
Hannig, F., Kuchcinski, K., Teich, J., & Wolinski, C. (2008). Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures. In Proceedings of the International Conference on Field Programmable Logic and Applications (pp. 391-396). Heidelberg, DE: New York: IEEE Press.

MLA:
Hannig, Frank, et al. "Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures." Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Heidelberg New York: IEEE Press, 2008. 391-396.

BibTeX: 

Zuletzt aktualisiert 2018-09-08 um 22:24