Output Serialization for FPGA-based and Coarse-grained Processor Arrays

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Hannig F, Teich J
Titel Sammelwerk: Proceedings of the 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'05
Jahr der Veröffentlichung: 2005
Tagungsband: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms
Seitenbereich: 78-84
ISBN: 1-932415-74-2


Abstract


This paper deals with the mapping of loop programs onto processor arrays either implemented in an FPGA or available as (reconfigurable) coarse-grained processor architectures. Usually the proportion of processing elements to I/O-interfaces is much higher whereby problems of data transportation and synchronization are arising. In this realm, we propose a systematic approach in order to feed-out data. Here, (a) an efficient routing strategy is presented and (b) a novel retiming strategy is given in order to ensure collision free output serialization.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Hannig, F., & Teich, J. (2005). Output Serialization for FPGA-based and Coarse-grained Processor Arrays. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (pp. 78-84). Las Vegas, NV, US.

MLA:
Hannig, Frank, and Jürgen Teich. "Output Serialization for FPGA-based and Coarse-grained Processor Arrays." Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA ), Las Vegas, NV 2005. 78-84.

BibTeX: 

Zuletzt aktualisiert 2018-09-08 um 21:55