Regular Mapping for Coarse-grained Reconfigurable Architectures

Hannig F, Dutta H, Teich J (2004)

Publication Type: Conference contribution

Publication year: 2004

Edited Volumes: ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Book Volume: V

Pages Range: 57-60

Conference Proceedings Title: Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing

Event location: Montreal, Quebec CA

ISBN: 0-7803-8484-9

Abstract

Similar to programmable devices such as processors or micro controllers also reconfigurable logic devices can be built as software, by programming the configuration of the device. In this paper, we present an overview of constraints which have to be considered when mapping applications to coarse-grained reconfigurable architectures. The application areas of most of these architectures addressing computational-intensive algorithms like video and audio processing or wireless communication. Therefore, reconfigurable arrays are in direct competition with DSP processors which are traditionally used for digital signal processing. Hence, existing mapping methodologies are closely related to approaches from the DSP world. They try to employ pipelining and temporal partitioning but they do not exploit the full parallelism of a given algorithm and the computational potential of typically 2-dimensional arrays. We present a first case study for mapping regular algorithms onto reconfigurable arrays by using our design methodology which is characterized by loop parallelization in the polytope model. The case study shows that our regular mapping methodology may lead to highly efficient implementations taking the constraints of the architecture into account.

Authors with CRIS profile

Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Hritam Dutta Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011 Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

How to cite

APA:

Hannig, F., Dutta, H., & Teich, J. (2004). Regular Mapping for Coarse-grained Reconfigurable Architectures. In Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing (pp. 57-60). Montreal, Quebec, CA.

MLA:

Hannig, Frank, Hritam Dutta, and Jürgen Teich. "Regular Mapping for Coarse-grained Reconfigurable Architectures." Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP ), Montreal, Quebec 2004. 57-60.

BibTeX: Download