Dynamic Piecewise Linear/Regular Algorithms

Hannig F, Teich J (2004)

Publication Type: Conference contribution

Publication year: 2004

Edited Volumes: International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004

Pages Range: 79 - 84

Conference Proceedings Title: Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004)

Event location: Dresden DE

ISBN: 0-7695-2080-4

Abstract

In this paper we present an extension of the class of piece-wise linear algorithms (PLAs) in order to model one type of dynamic data dependencies. This extension significantly increases the range of applications which can be parallelized and mapped to massively parallel processor arrays. For instance, a lot of computational intensive applications for video and image processing consist of nested loop programs with only few and simple run-time dependent conditionals. Furthermore, we outline in which case these extensions can directly used - with slight changes - within traditional mapping methodologies based on loop parallelization in the polytope model. Additionally, we outline future research directions in the case existing methods will be inefficient.

Authors with CRIS profile

Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011 Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

How to cite

APA:

Hannig, F., & Teich, J. (2004). Dynamic Piecewise Linear/Regular Algorithms. In Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004) (pp. 79 - 84). Dresden, DE.

MLA:

Hannig, Frank, and Jürgen Teich. "Dynamic Piecewise Linear/Regular Algorithms." Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC ), Dresden 2004. 79 - 84.

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