Dynamic Piecewise Linear/Regular Algorithms

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Hannig F, Teich J
Titel Sammelwerk: International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004
Jahr der Veröffentlichung: 2004
Tagungsband: Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004)
Seitenbereich: 79 - 84
ISBN: 0-7695-2080-4


Abstract


In this paper we present an extension of the class of piece-wise linear algorithms (PLAs) in order to model one type of dynamic data dependencies. This extension significantly increases the range of applications which can be parallelized and mapped to massively parallel processor arrays. For instance, a lot of computational intensive applications for video and image processing consist of nested loop programs with only few and simple run-time dependent conditionals. Furthermore, we outline in which case these extensions can directly used - with slight changes - within traditional mapping methodologies based on loop parallelization in the polytope model. Additionally, we outline future research directions in the case existing methods will be inefficient.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Hannig, F., & Teich, J. (2004). Dynamic Piecewise Linear/Regular Algorithms. In Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004) (pp. 79 - 84). Dresden, DE.

MLA:
Hannig, Frank, and Jürgen Teich. "Dynamic Piecewise Linear/Regular Algorithms." Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC ), Dresden 2004. 79 - 84.

BibTeX: 

Zuletzt aktualisiert 2018-09-08 um 21:54