A Joined Architecture/Compiler Environment for ASIPs

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Fischer D, Teich J, Trinkert S, Weper R
Titel Sammelwerk: Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems
Jahr der Veröffentlichung: 2000
Tagungsband: ACM SIG Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Seitenbereich: 26 - 33


Abstract


In this paper, we introduce a methodology for rapid prototyping of application-specific instruction set processors (ASIPs) including the automatic generation of bit-true and cycle-accurate instruction-set simulators and corresponding compiler (re)targets. The methodology is based on ASMs (abstract state machines) as the underlying formal model for describing a processor's behavior. We explain the major advantages of using ASMs and outline the main tool flow from graphical entry of a processor's major RTL building blocks and simulator generation as well as the current status of our project.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Einrichtungen weiterer Autorinnen und Autoren

Universität Paderborn


Zitierweisen

APA:
Fischer, D., Teich, J., Trinkert, S., & Weper, R. (2000). A Joined Architecture/Compiler Environment for ASIPs. In ACM SIG Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems (pp. 26 - 33). San Jose, CA, US.

MLA:
Fischer, Dirk, et al. "A Joined Architecture/Compiler Environment for ASIPs." Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2000),, San Jose, CA 2000. 26 - 33.

BibTeX: 

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