Bitstream Decompression for High Speed FPGA Configuration from Slow Memories

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Koch D, Beckhoff C, Teich J
Titel Sammelwerk: ICFPT 2007 - International Conference on Field Programmable Technology
Verlag: IEEE Press
Verlagsort: New York
Jahr der Veröffentlichung: 2007
Tagungsband: Proc. of the IEEE International Conference on Field-Programmable Technology 2007
Seitenbereich: 161-168


Abstract


In this paper, we present hardware decompression accelerators for bridging the gap between high speed FPGA configuration interfaces and slow configuration memories. We discuss different compression algorithms suitable for a decompression on FPGAs as well as on CPLDs with respect to the achievable compression ratio, throughput, and hardware overhead. This leads to various decompressor implementations with one capable to decompress at high data rates of up to 400 megabytes per second while only requiring slightly more than a hundred look-up tables. Furthermore, we present a sophisticated configuration bitstream benchmark. © 2007 IEEE.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Koch, D., Beckhoff, C., & Teich, J. (2007). Bitstream Decompression for High Speed FPGA Configuration from Slow Memories. In Proc. of the IEEE International Conference on Field-Programmable Technology 2007 (pp. 161-168). Kokurakita, Kitakyushu, JP: New York: IEEE Press.

MLA:
Koch, Dirk, Christian Beckhoff, and Jürgen Teich. "Bitstream Decompression for High Speed FPGA Configuration from Slow Memories." Proceedings of the IEEE International Conference on Field-Programmable Technology 2007 (ICFPT'07), Kokurakita, Kitakyushu New York: IEEE Press, 2007. 161-168.

BibTeX: 

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