Hierarchical Partitioning for Piecewise Linear Algorithms

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Dutta H, Hannig F, Teich J
Titel Sammelwerk: PARELEC 2006 - Proceedings: International Symposium on Parallel Computing in Electrical Engineering
Jahr der Veröffentlichung: 2006
Tagungsband: Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering
Seitenbereich: 153-160
ISBN: 978-0-7695-2554-9


Abstract


Processor arrays are used as accelerators for plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor array architectures has lead to demand for mapping tools to realize the full potential of these architectures. Such architectures are characterized by hierarchies of parallelism and memory structures, i.e. processor array apart from different levels of cache arrays have a number of processing elements (PE) where each PE can further contain sub-word parallelism. In order to handle large scale problems, balance local memory requirements with I/O-bandwidth, and use different hierarchies of parallelism and memory, one needs a sophisticated transformation called hierarchical partitioning. In this paper, we introduce for the first time a detailed methodology encompassing hierarchical partitioning. © 2006 IEEE.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Dutta, Hritam
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Dutta, H., Hannig, F., & Teich, J. (2006). Hierarchical Partitioning for Piecewise Linear Algorithms. In Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering (pp. 153-160). Bialystok, PL.

MLA:
Dutta, Hritam, Frank Hannig, and Jürgen Teich. "Hierarchical Partitioning for Piecewise Linear Algorithms." Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering (PARELEC), Bialystok 2006. 153-160.

BibTeX: 

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