Hierarchical Partitioning for Piecewise Linear Algorithms

Dutta H, Hannig F, Teich J (2006)

Publication Type: Conference contribution

Publication year: 2006

Edited Volumes: PARELEC 2006 - Proceedings: International Symposium on Parallel Computing in Electrical Engineering

Pages Range: 153-160

Conference Proceedings Title: Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering

Event location: Bialystok PL

ISBN: 978-0-7695-2554-9

DOI: 10.1109/PARELEC.2006.43

Abstract

Processor arrays are used as accelerators for plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor array architectures has lead to demand for mapping tools to realize the full potential of these architectures. Such architectures are characterized by hierarchies of parallelism and memory structures, i.e. processor array apart from different levels of cache arrays have a number of processing elements (PE) where each PE can further contain sub-word parallelism. In order to handle large scale problems, balance local memory requirements with I/O-bandwidth, and use different hierarchies of parallelism and memory, one needs a sophisticated transformation called hierarchical partitioning. In this paper, we introduce for the first time a detailed methodology encompassing hierarchical partitioning. © 2006 IEEE.

Authors with CRIS profile

Hritam Dutta Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011 Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

How to cite

APA:

Dutta, H., Hannig, F., & Teich, J. (2006). Hierarchical Partitioning for Piecewise Linear Algorithms. In Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering (pp. 153-160). Bialystok, PL.

MLA:

Dutta, Hritam, Frank Hannig, and Jürgen Teich. "Hierarchical Partitioning for Piecewise Linear Algorithms." Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering (PARELEC), Bialystok 2006. 153-160.

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