Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays

Hannig F, Merker R, Siegel S, Teich J (2006)

Publication Type: Conference contribution

Publication year: 2006

Journal

Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems

Edited Volumes: Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems

Pages Range: 71-76

Conference Proceedings Title: Proceedings of the 18th International Conference on Parallel and Distributed Computing and Systems

Event location: Dallas, TX US

ISBN: 0-88986-638-4

Abstract

Methods for an efficient mapping of algorithms to parallel architectures are of utmost importance because many state-of-the-art embedded digital systems deploy parallelism to increase their computational power. This paper deals with the mapping of loop programs onto processor arrays implemented in an FPGA or available as (reconfigurable) coarsegrained processor architectures. Most existing work is closely related to approaches from the DSP domain and is not able to exploit the full parallelism of a given algorithm and the computational potential of a typical 2-dimensional array. In contrast, we present a mapping methodology which incorporates many important parameters of the target architecture in one approach. These are: number of processing elements, resources of the data path and memory within a processing element, and interconnection within the processor array. Based on these parameters, we formulate an optimization problem whose solution specifies an efficient mapping of an algorithm to the target architecture. We can optimize for speed of the algorithm and/or hardware cost caused by the communication and computation resources of the architecture.

Authors with CRIS profile

Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011 Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

Involved external institutions

Technische Universität Dresden DE Germany (DE)

How to cite

APA:

Hannig, F., Merker, R., Siegel, S., & Teich, J. (2006). Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays. In Proceedings of the 18th International Conference on Parallel and Distributed Computing and Systems (pp. 71-76). Dallas, TX, US.

MLA:

Hannig, Frank, et al. "Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays." Proceedings of the 18th International Conference on Parallel and Distributed Computing and Systems (PDCS), Dallas, TX 2006. 71-76.

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