A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Dutta H, Hannig F, Heigl B, Hornegger H, Teich J
Titel Sammelwerk: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Verlag: Institute of Electrical and Electronics Engineers
Jahr der Veröffentlichung: 2006
Tagungsband: Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors
Seitenbereich: 331-337
ISBN: 978-0-7695-2682-9
ISSN: 1063-6862


Abstract


Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a state-of-the-art algorithm in medical imaging, which falls in the class of 2D adaptive filter algorithms. In this paper, we propose a semi-automatic mapping methodology for the generation of hardware accelerators for such a generic class of adaptive filtering applications in image processing. The final architecture deliver similar synthesis results as a hand-tuned design. © 2006 IEEE.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Dutta, Hritam
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Einrichtungen weiterer Autorinnen und Autoren

Siemens AG, Healthcare Sector


Zitierweisen

APA:
Dutta, H., Hannig, F., Heigl, B., Hornegger, H., & Teich, J. (2006). A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. In Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors (pp. 331-337). Steamboat Springs, CO, US: Institute of Electrical and Electronics Engineers.

MLA:
Dutta, Hritam, et al. "A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing." Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors (ASAP), Steamboat Springs, CO Institute of Electrical and Electronics Engineers, 2006. 331-337.

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