Automatic and Optimized Generation of Compiled High-Speed RTL Simulators

Beitrag bei einer Tagung


Details zur Publikation

Autor(en): Hannig F, Kupriyanov O, Teich J
Jahr der Veröffentlichung: 2004
Tagungsband: Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004)


FAU-Autoren / FAU-Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Hannig, F., Kupriyanov, O., & Teich, J. (2004). Automatic and Optimized Generation of Compiled High-Speed RTL Simulators. In Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004). Washington, DC, US.

MLA:
Hannig, Frank, Olexiy Kupriyanov, and Jürgen Teich. "Automatic and Optimized Generation of Compiled High-Speed RTL Simulators." Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004), Washington, DC 2004.

BibTeX: 

Zuletzt aktualisiert 2018-07-08 um 21:39