A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template

Conference contribution


Publication Details

Author(s): Kissler D, Hannig F, Kupriyanov O, Teich J
Publication year: 2006
Conference Proceedings Title: Proceedings of the 2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC)
Pages range: 31-37


FAU Authors / FAU Editors

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


How to cite

APA:
Kissler, D., Hannig, F., Kupriyanov, O., & Teich, J. (2006). A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. In Proceedings of the 2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC) (pp. 31-37).

MLA:
Kissler, Dmitrij, et al. "A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template." Proceedings of the 2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC) 2006. 31-37.

BibTeX: 

Last updated on 2018-23-11 at 06:05